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 MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit ECL/TTL Load Reducing DRAM Driver
The MC10H/100H660 is a 4-bit ECL input, translating DRAM address driver, ideally suited for driving TTL compatible DRAM inputs from an ECL system. It is designed for use in high capacity, highly interleaved DRAM memory boards, that directly interface to a high speed, pipelined ECL bus interface, where new operations may be initiated to the board at up to a 50 MHz rate. The latch provides the capability for the memory controller to propagate new addresses to different banks without having to wait for the address timing constraints to be satisfied from a previous memory operation. The dual output fanout reduces input loading from the controller by a factor of two, thus significantly improving board etch propagation delays from the controller, without the need for additional ECL buffering. The H660 features special TTL outputs which do not have an IOS limiting resistor, therefore allowing rapid charging of the load capacitance. Output voltage levels are designed specifically for driving DRAM inputs. The output stages feature separate power and ground pins to isolate output switching noise from internal circuitry, and also to improve simultaneous switching performance. The 10H version is compatible with MECL 10H ECL logic levels. The 100H version is compatible with 100K levels. * * * * High Capacitive Drive Outputs to Drive DRAM Address Inputs Extra TTL and ECL Power/Ground Pins to Minimize Switching Noise Dual Supply 10.7 ns Max. D to Q into 300 pF
MC10H660 MC100H660
FN SUFFIX PLASTIC PACKAGE CASE 776-02
LOGIC SYMBOL
ECL Inputs VEE VCCE D0 IVT01 IGND01 D EN R Q DRAM Driver Outputs Q0A OGND0 Q0B OVT01 Q1A D EN R Q OGND1 Q1B
PIN NAMES
PIN OGND[0:3] OVT01, OVT23 IGND01, IGND23 IVT01, IVT23 VEE VCCE D[0:3] Q[0:3]A, Q[0:3]B LEN R FUNCTION Output Ground (0V) Output VCCT (+5.0 V) Internal TTL Ground (OV) Internal TTL VCCT (+5.0 V) ECL Neg. Supply (-5.2/ -4.5 V) ECL Ground (0V) Data Inputs (ECL) Data Outputs (TTL levels) Latch Enable (ECL) Reset (ECL) OGND2 OVT23 OGND3
D1
Q2A D2 IVT23 IGND23 D3 D EN R LEN Q D EN R Q OGND2 Q2B OVT23 Q3A OGND3 Q3B
Q2A
Q2B
Q3A
25 Q1B OGND1 Q1A OVT01 Q0B OGND0 Q0A 26 27 28 1 2 3 4 5 IVT01
24
23
22
21
20
19 18 17 16 IVT23 IGND23 VCCE VCCE D3 D2 R R
Q3B
Pinout: 28-Lead PLCC 15 (Top View)
14 13 12 6 IGND01 7 VEE 8 VEE 9 D0 10 D1 11 LEN
TRUTH TABLE
D L H X X LEN H H L X R L L L H Q L H Q0 L
3/93
(c) Motorola, Inc. 1996
2-121
REV 5
MC10H660 MC100H660
DC CHARACTERISTICS: VCCT = 5.0 V 10%; VEE = - 5.2 V 5% (10H version); VEE = - 4.2 V to -5.5 V (100H version)
0C Symbol IEE ICCH ICCL Characteristic Power Supply Current ECL TTL min max 41.8 77.0 94.6 min 25C max 44.0 77.1 95.7 min 85C max 46.2 79.2 96.8 Unit mA mA mA Condition
TTL CHARACTERISTICS: VCCT = 5.0 V 10%; VEE = - 5.2 V 5% (10H version); VEE = - 4.2 V to -5.5 V (100H version)
0C Symbol VOH VOL IOS Characteristic Output HIGH Voltage Output LOW Voltage Output Short Circuit Current* min 2.6 0.50 * max min 2.6 0.50 * 25C max min 2.6 0.50 * 85C max Unit V V V Condition IOH = - 24 mA IOL = 24 mA See Note 1
1. The outputs must not be shorted to ground, as this will result in permanent damage to the device. The high drive outputs of this device do not include a limiting IOS resistor. Minimum recommended load capacitance is 100 pF. Precise output performance and waveforms will depend on the exact nature of the actual load. The lumped load is of course an approximation to a real memory system load.
AC Characteristics: VCCT = 5.0 V 10%; VEE = - 5.2 V 5% (10H version) VEE = - 4.2 V to -5.5 V (100H version)
0C Symbol ts tn tw(H) tR tF tPLH tPHL Characteristic Set-up Time, D to LEN Hold Time, D to LEN LEN Pulse Width, HIGH Output Rise/Fall Time 0.8 V - 2.0 V Propagation Delay to Output 50% point of ECL input to 1.5 V point of TTL output tPHL Propagation Delay to Output Propagation Delay to Output 50% point of ECL input to 2.4 V point of TTL output tPHL Propagation Delay to Output 50% point of ECL input to 0.8 V point of TTL output D min 0.5 1.5 2.0 0.5 3.0 4.0 4.5 4.3 4.9 5.4 4.1 4.5 5.0 3.9 4.8 5.8 4.7 5.5 6.3 4.5 6.0 7.0 4.0 4.9 6.0 4.3 6.1 7.2 2.0 6.0 8.0 9.5 6.9 8.9 10.4 9.1 8.5 10.0 5.9 7.2 8.8 7.1 8.3 9.5 6.7 9.0 10.6 6.0 7.3 9.0 6.5 9.1 10.8 max min 0.5 1.5 2.0 0.5 3.0 4.0 4.5 4.3 4.9 5.4 4.1 4.5 5.0 3.9 4.8 5.8 4.7 5.5 6.3 4.5 6.0 7.0 4.0 4.9 6.0 4.3 6.1 7.2 2.0 6.0 8.0 9.5 6.9 8.9 10.4 9.1 8.5 10.0 5.9 7.2 8.8 7.1 8.3 9.5 6.7 9.0 10.6 6.0 7.3 9.0 6.5 9.1 10.8 25C max min 0.5 1.5 2.0 0.5 3.0 4.0 4.5 4.3 4.9 5.4 4.1 4.5 5.0 4.0 5.0 5.9 4.8 5.6 6.4 4.4 6.0 6.9 4.0 4.9 5.9 4.3 6.1 7.2 2.0 6.0 8.0 9.5 6.9 8.9 10.4 9.1 8.5 10.0 6.1 7.4 8.9 7.2 8.4 9.6 6.6 9.0 10.3 6.0 7.3 8.9 6.5 9.1 10.8 85C max Unit ns ns ns ns ns CL = 200 pF CL = 100 pF CL = 200 pF CL = 300 pF CL = 100 pF CL = 200 pF CL = 300 pF CL = 100 pF CL = 200 pF CL = 300 pF CL = 100 pF CL = 200 pF CL = 300 pF CL = 100 pF CL = 200 pF CL = 300 pF CL = 100 pF CL = 200 pF CL = 300 pF CL = 100 pF CL = 200 pF CL = 300 pF CL = 100 pF CL = 200 pF CL = 300 pF Condition
LEN
ns
R
ns
tPLH
D
ns
LEN
ns
D
ns
LEN
ns
R
ns
MOTOROLA
2-122
MECL Data DL122 -- Rev 6
MC10H660 MC100H660
OUTPUT STRUCTURE - Output Q0A Structure Shown POWER VS FREQUENCY - typical
INTERNAL TTL POWER
IVT01 OVT01
700 600
POWER VS FREQUENCY PER BIT PDYNAMIC = CL VSWING VCC PTOTAL = PSTATIC + PDYNAMIC
500 Power, mW 400 300 200 100 OGND0 INTERNAL TTL GROUND IGND01 0 0 20 40 60 FREQUENCY, MHZ 80 100 120 300 PF 200 PF 100 PF 50 PF NO LOAD
Q0A
10H ECL DC Characteristics: VCCT = 5.0 V 10%; VEE = - 5.2 V 5%
0C Symbol S bl IIH IIL VIH VIL Characteristic Ch ii Input HIGH Current Input LOW Current Input HIGH Voltage Input LOW Voltage min 1.5 -1170 -1950 - 840 -1480 max 225 1.0 -1130 -1950 - 810 -1480 min 25C max 145 1.0 -1060 -1950 - 720 -1445 min 85C max 145 Unit Ui A A mV mV Condition C di i
100H ECL DC Characteristics: VCCT = 5.0 V 10%; VEE = - 4.2 V to - 5.5 V
0C Symbol S bl IIH IIL VIH VIL Characteristic Ch ii Input HIGH Current Input LOW Current Input HIGH Voltage Input LOW Voltage min 1.5 -1165 -1810 - 880 -1475 max 225 1.0 -1165 -1810 - 880 -1475 min 25C max 145 1.0 -1165 -1810 - 880 -1475 min 85C max 145 Unit Ui A A mV mV Condition C di i
MECL Data DL122 -- Rev 6
2-123
MOTOROLA
MC10H660 MC100H660
AC TEST SET-UP
CL = 100 pF 450 D.U.T. B 100 PF 50
PULSE GEN.
A 50
SCOPE
The MC10H/100 H660 ECL-TTL DRAM Address Driver
The MC 10H/100H660 was designed for use in high capacity, highly interleaved DRAM memory boards, that directly interface to a high speed, pipelined ECL bus interface, where new operations may be initiated to the board at a 50 MHz rate ( e.g. bipolar RISC systems). The following briefly discusses the major design features of the part over existing semiconductor devices traditionally used in interfacing DRAMs in high performance system environments. 1. ECL Translator High performance memory systems of the past that were interfaced to ECL buses had to rely on separate ECL translators and DRAM drivers to interface to large DRAM arrays, which is acceptable if the module is not highly interleaved and the bus cycle time is comparable to the DRAM access time. This becomes inadequate as the cycle time of the interface becomes significantly faster than the address timing requirements of the RAM, and as the degree of internal board interleaving increases. These higher performance demands require that the internal address and control signals propagated to the DRAM drivers be implemented in ECL, thus requiring the integration of the driver and translator functions. Integration of the translator/drive function also reduces access latency, as well as keeping DRAM timing parameters from being violated, due to the excessive delays encountered with separate parts. 2. MOS Drive Capacity Outputs are specifically designed for driving large numbers of DRAMs ([300 pF), which reduce the number of parts and power requirements needed per board. Output voltage levels are designed specifically for driving DRAM inputs. No ECL translator parts on the market today provide the designer with this drive capability as well as the flexibility to vary the number of DRAMs that are driven by the part. 3. Transparent Latch The latch is added to provide the capability for a memory controller to propagate new addresses to different banks without having to wait for the address timing constraints to be satisfied from a previous memory operation. For system implementations where this is acceptable, the user has the capability to keep the latch open, thus having the part act as an address translator/buffer, with minimal performance impact due to the additional propagation delay incurred from the internal latch. The latch is controlled within an already existing DRAM timing signal. 4. 1:2 Output Fanout This function is useful in that it reduces input loading from the controller by a factor of two, thus significantly improving board etch propagation delays from the controller to the large number of translators, without the addition of ECL glue logic parts to reduce the loading. In large memory boards, so many translators are needed that this type of organization is not a handicap. 5. Low Skew, Low Propagation Delay Low skew of the part as well as fast propagation delay enable faster overall DRAM operation to be attained than is possible with existing parts. 6. Power and Package Pin Layout The H660 is specifically designed with additional power and ground pins to greatly improve simultaneous switching performance over existing driver parts.
MOTOROLA
2-124
MECL Data DL122 -- Rev 6
MC10H660 MC100H660
OUTPUT WAVEFORMS
simulated
Example 1. An output load consisting of just CL = 50 pF results in overshoot at the output Q:
8
6
Q
VOLTAGE
4
2
0 D -2 0 25 TIME 50 75
Example 2. In a memory system application, use of an external source resistor is suggested. Simulations run with RS = 8 and CL = 300pF leads to clean waveforms both at the output, Q, and at point Qp:
Q
RS = 8
QP
H660 OUTPUT
CL = 300pF
8 6 4 VOLTAGE Q 2 QP 0 -2 0 25 TIME 50 75 D
MECL Data DL122 -- Rev 6
2-125
MOTOROLA
MC10H660 MC100H660
OUTLINE DIMENSIONS
FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE D
B -N- Y BRK U D Z -L- -M- 0.007 (0.180)
M
0.007 (0.180)
M
T L-M
S
N
S S
T L-M
N
S
W
28 1
D
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
V
A Z R C
0.007 (0.180) 0.007 (0.180)
M
T L-M T L-M
S
N N
S
H
0.007 (0.180)
M
T L-M
S
N
S
M
S
S
E 0.004 (0.100) G G1 0.010 (0.250)
S
K1
J
-T- VIEW S
SEATING PLANE
K F VIEW S 0.007 (0.180)
M
T L-M
S
N
S
T L-M
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
MOTOROLA
2-126
MECL Data DL122 -- Rev 6
MC10H660 MC100H660
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MECL Data DL122 -- Rev 6 2-127
*MC10H660/D*
MC10H660/D MOTOROLA


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